1 Bit – Adders

Half Adder:

Halfadder

Truth table:

HA-TRUTH-TABLE

Program:

Structural:


module ha_str(
output s, co,
input a, b);
xor u1(s, a, b);
and u2(co, a, b);
endmodule


Dataflow:


module ha_dat(
output s, co,
input a, b);
assign {co, s} = a + b; /* RTL addition operator. Gives two bits output when two single bits are added, hence MSB goes to carry, LSB is sum. We can do like this also………….. assign s = a ^ b, co = a & b; this will be same  as gate level modelling..
*/
endmodule


Behavioral:


module ha_beh(
output reg s, co,
input a, b);
always @({b, a}) begin
case ({b, a})
2’b00: begin s = 0; co = 0; end
2’b01: begin s = 1; co = 0; end
2’b10: begin s = 1; co = 0; end
2’b11: begin s = 0; co = 1; end
endcase

end
endmodule


Full Adder:

Fulladder

Truth table:

TruthTable_1bit_adder_yz

Program:

Dataflow:


module fa_dat(
output s, co,
input a, b, ci);
assign {co, s} = a + b + ci;
endmodule


Structural:


module fa_str(
output s, co,
input a, b, ci);
wire s1, c1, c2;
/*Structural Modelling: Instantiate Half Adder modules as shown in diagram. It is like calling already created module. Creating full adder with two half adders*/
ha_str ha_1 (.s(s1), .co(c1), .a(b), .b(ci));
ha_str ha_2 (.s(s), .co(c2), .a(a), .b(s1));
/* ha_str is module name, ha_1, ha_2 are instance names. Every instance has different name*/
or (co, c1, c2);
endmodule


Behavioral:


module fa_beh(
output reg s, co,
input a, b, ci);
always @(a, b, ci)
case ({ci, b, a})
3’b000: begin s = 0; co = 0; end
3’b001: begin s = 1; co = 0; end
3’b010: begin s = 1; co = 0; end
3’b011: begin s = 0; co = 1; end
3’b100: begin s = 1; co = 0; end
3’b101: begin s = 0; co = 1; end
3’b110: begin s = 0; co = 1; end
3’b111: begin s = 1; co = 1; end
endcase
endmodule


Content Created: 17/06/2017
Content Updated: 25/06/2017.

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