Below is the schematic diagram of 4 bit Ripple Carry Adder.

Ripple Carry adder is a series of cascaded Full Adders. The number of Full Adders required to make the Ripple Carry Adder depends on the number of bits required to perform the addition of the two numbers.

For example, addition of two 4 bit numbers, require 4 Full Adders in a Ripple Carry Adder .

The Carry Out (co; as shown symbolically in the diagram) from 1st-bit full adder is sent to Carry In (ci; as shown symbolically in the diagram) of the 2nd-bit full adder. The Carry propagates from lower bits to higher bits, hence it is named “Ripple Carry Adder”.

Program: To write a Verilog code to write a 4 bit Ripple Carry Adder using Full Adders: Structural Modelling using Full-adders.

output [3:0] s, /* 4-bit vector sum s[3] to s[0] */
output co,
input [3:0] a, b, /* 4-bit vector inputs */
input ci);
wire c1, c2, c3; /* create internal wires to connect modules for carry propagation from lower bits to higher bits. Refer block diagram for explanation */
/*Structural Model: Instantiate Full Adder modules.*/
fa_str fa_0(s[0], c1, a[0], b[0], ci);
fa_str fa_1(s[1], c2, a[1], b[1], c1);
fa_str fa_2(s[2], c3, a[2], b[2], c2);
fa_str fa_3(s[3], co, a[3], b[3], c3);
endmodule

Program: n bit Ripple Carry Adder using Full Adder modules and generate statement. To make n-bit ripple carry adder, we use generate block to implement a Full Adder module n times, where n is an integer.

module adder #(parameter n = 8 /*parameter initialisation to 8*/)(
output [n:0] s, /* n+1 bit sum, output carry gets concatenated to MSB of sum */
input [n-1:0] a, b /* n bit inputs */
input ci);
wire [n:0] c; /* internal carry propagating wire */
genvar i; /* variable used inside generate block */
assign c[0] = ci, /* initial carry is input carry */
s[n] = c[n]; /* final carry goes to MSB of sum */
generate /* This is how full adder in generated n times */
fa_str fa_1(s[i], c[i+1], a[i], b[i], c[i]); end
endgenerate
endmodule

The fa_str module instance in above programs relates to another Verilog module.

Every digital circuit has delay in operation time. Each Full Adder has a specific range of delay.

The propagation of Carry from lower bit Full Adder to higher bit Full Adders in Ripple Carry Adder causes delay in generating final Sum bit.

Output depends on the number of bits or Full Adders in the circuit. With an increase in number of bits, the delay increases too.

Therefore with increase in combinational delay leads to decrease in operating frequency.

To overcome this disadvantage, we use