What do we do when we want to make a counter? We will draw its schematic and wire it up using a breadboard or a PCB and check its functionality. This approach is good for small circuits but for a larger circuit, it is not possible to follow this approach since it becomes expensive and inefficient.
Instead of wiring the hardware physically, we wire up the hardware using Verilog. Using Verilog we can write a code which describes the hardware we intend to make and then simulate it using a Verilog simulator. Using the simulation results we can check whether our approach to building the hardware was correct or not.
If not then we can do some adjustments and re-run the simulation. This approach is both time and cost-effective and we can play around with different approaches.
After we have written the Verilog code for our hardware and verified its simulation result we are ready to synthesize it.
Our written code must be able to resemble the target hardware. we apply this Verilog code as an input to a synthesis tool such as
(i) Cadence Genus
(ii) Cadence RC compiler
(iii) Xilinx Vivado
The tool generates the synthesized netlist. The tool has a list of library components like D -Flip Flop, Counters, shifters etc. Suppose the Verilog code has a D Flip Flop code written in it, the synthesis tool will place a D Flip Flop from its list of library components.
This approach followed by the tool is called as synthesis and is followed for rest of the Verilog code written by you. After the tool is done synthesizing it will generate another Verilog file called as a synthesized netlist file.
This netlist file is the sent further for Verification, timing checks, Floor-Planning, Layout etc.
The “Veri” part of the name is short for verification, and Verilog was designed for simulating digital hardware to verify that it operated correctly prior to fabrication.
Some of the language constructs pertain to board-level logic (e.g. tri-state buses), but it is mostly known as a digital IC modeling language. It was the “sign off” simulation language for chip design for many years, and still is in some quarters.
Verilog is a hardware description language. It is different from general purpose programming languages in that it is specifically used to model hardware.
In Verilog, you have the ability to specify registers, wires, gates, clock, etc. It is very useful when you have hardware specifications on paper, and you want to simulate and test it first before synthesizing the circuit, thus saving time and money.
The language is also pretty simple, only requires knowledge of digital logic, and it has a syntax similar to C.
Pradyuman R Bissa