Port Instantiation in Verilog.

Port Instantiation in Verilog
In Verilog, we can call other Verilog modules. For example, to build a Full Adder we can write a code for half adder. We call it 2-times to implement a full adder. This is called a granular approach and helps greatly in identifying bugs.

 

Half adder:


module HA( /* Half Adder code */
output sum, carry,
input a, b);
assign sum = a ^ b;  /* ^ stands for EX-OR operation */
assign carry = a & b; /* & stands for AND operation */
endmodule


Full adder:


module  FA(
output sum, carry,
input a, b, cin);
wire w1, w2, w3; /* Wires represent the internal connections as we use in below */
HA h1(w2, w1, a, b);
HA h2(sum, w3, w1, w2);
assign cout = w1 | w3; /* here | represents OR operation */
endmodule

Capture
Full Adders using Half Adders: Block Diagram

Here HA h1(w1,w2,a,b); implies that we are instantiating the HA module

w2 corresponds to the sum port in the HA

w1 corresponds to the carry port

a, b corresponds to the a, b in the HA module

So when we call this HA module from FA module then w1, w2, a, b of FA pass onto the HA module where they are operated upon the HA logic and returned to the FA.

h1 is the name of the instance, i.e h1 is the 1st Half Adder and h2 is the 2nd Half Adder.

An alternate way of writing this would be

HA h1(.sum(w2),.carry(w1),.a(a),.b(b));,

One advantage of writing in this fashion is that you can jumble the order in which you write the port name while instantiating, i.e.

HA h1(.carry(w1),.sum(w2),.b(b),.a(a));

is also same as above, but

HA h1(w1,w2,b,a); is NOT same

It will give erroneous output.

It’s a good practice to write port instances in .notations.

Pradyuman R Bissa

prady.bissa@gmail.com

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