The Structure of a Verilog code.

The basic structure of a Verilog code is,

module module_name(port names and directions);
……..
endmodule



module and_gate( /* and_gate is the name of the module */
output out,  /* out is the name of the output port */
input a, b); /* a,b are the inputs */
assign out = a & b; /* The actual logic */
endmodule /* Implies end of the Verilog code */


Pradyuman R Bissa

prady.bissa@gmail.com

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

Powered by WordPress.com.

Up ↑

%d bloggers like this: