Multiplexers

The objective is to learn different styles and techniques of coding in this post.
Program: To write a Verilog code for 2:1 Multiplexer.
K0BCg
Schematic Diagram of basic 2:1 Mux
Picture1
Truth table of basic 2:1 Mux

Structural: Gate-level modeling. The program resembles the block diagram shown above.


module mux21_str(
output y,
input a, b, s);
wire w1, w2;
and (w1, a, ~s);
and (w2, b, s);
or (y, w1, w2);
endmodule


 


module mux21_dat(
output y,
input a, b, s); /*s is select line, a, b are inputs*/
assign y = s?b:a; /* Conditional operator in verilog. If s=1 then y=b else if s=0 then y=a.*/
endmodule


We can perform data flow modeling like above.

Dataflow: Using logical expressions.


module mux21_dat(
output y,
input a, b, s); /*s is select line, a, b are inputs*/
assign y = (~s & a) | (s & b); /* Direct Logic expression, resembles Gate level modelling */
endmodule


Behavioral: Based on the truth table.


module mux21_beh(
output reg y,
input a, b, s);
always@(*)
case(s)
0: y = a; /* if s = 0, y = a */
1: y = b; /* if s = 1, y = b */
default y = 0; /*every case block should contain a default case*/
endcase
endmodule


Now we see different styles and techniques in the programming.

Program: To write a Verilog code for 4:1 Multiplexer by Behavioral Modellingwithout using a case statement.

The Enable pin is included.

This technique makes programming very easy. This type of code can be extended to higher bit multiplexer, without changing the main statement.

The bit widths of inputs a and selection s need to be changed. But if we use a case statement, the program becomes inefficient.


module mux41_beh(
output reg y,
input [3:0] a,
input [1:0] s,
input en);
always @(*) /* A “*” in sensitivity list means all of the inputs are included in the list */
if (en) /* enable pin for mux, only if en = 1, the below logic is executed */
y = a[s];
/* This is one tactic in programming.
So y = a[s] implies that if s = 0, y = a[0],
and simliar for other values of s, s = 2 or 2’b10, y = a[2]. */
else y = 0;
endmodule

The statement y = a[s]; is same for any multiplexer like 8:1 or 16:1 or 32:1 or even more.


 

Program: To write a Verilog code for Mux 8:1 in data flow using an extension of the conditional operator.


module mux81_dat(
output y,
input [7:0] a,
input [2:0] s);
assign y = (s==0)? a[0]:
(s==1)? a[1]:
(s==2)? a[2]:
(s==3)? a[3]:
(s==4)? a[4]:
(s==5)? a[5]:
(s==6)? a[6]: a[7];
/* This is called extention of conditional operator.
We can extend it as many times as we want */
endmodule


 

Now we will see how to do higher bit muxes using lower bit muxes in Structural Modelling.

Picture3
Schematic of a 4:1 Mux using three 2:1 muxers

Program: To write a Verilog code for 4:1 Mux using three 2:1 Muxes.


module mux41_str(
output y,
input [3:0] a,
input [1:0] s);
wire w1, w2;
mux21_str u1(w1, a[0], a[1], s[0]);
mux21_str u2(w2, a[2], a[3], s[0]);
mux21_str u3(y, w1, w2, s[1]);
endmodule


Program: To write a Verilog code for 8:1 Mux using two 4:1 Muxes, and one 2:1 Mux.


module mux81_str(
output y,
input [7:0] a,
input [2:0] s);
wire w1, w2;
mux41_str u1(w1, a[7:4], s[1:0]);
mux41_str u2(w2, a[3:0], s[1:0]);
mux21_str u3(y, w2, w1, s[2]);
endmodule



Content Created: 27/06/2017


 

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