2:4 Decoder:

Program: To write a Verilog code for a 2:4 Decoder Structural/Gate level modeling: This is in context of the schematic diagram shown above.

module dec24_str(
output [3:0] y,
input [1:0] a,
input en);
and (y[0], ~a[1], ~a[0], en); /* 3-input AND gates */
and (y[1], ~a[1], a[0], en);
and (y[2], a[1], ~a[0], en);
and (y[3], a[1], a[0], en);
endmodule

Program: To write a Verilog code for 2:4 Decoder in dataflow modeling.

A shifting operator is used to make the program in a single line.

Otherwise, we can use assign statements to use logical operators to create logical expressions of the decoder.

This code can be used for any size decoder like 3:8, or 4:16 or even higher.

(Credits: E Sagar)

module dec24_dat(
output [3:0] y,
input [1:0] a,
input en);
assign y = en ? (4’b0001 << a) : 0;
endmodule

We used left-shifting operator inside a conditional operator.

when en = 1 and a = 0, y = 0001,

else if a = 1 then y = 0010,

else if a = 2 then y = 0100,

else if a = 3 then y = 1000.

en = 0, y = 0000.

4’b” is a representation of binary in Verilog. If the decoder size has to be increased, let’s say for 3:8 decoder, then we change the assign statement like this:

assign y = en ? (8’b000000001 << a) : 0;
/* or simply */ assign y = en ? (1 << a) : 0;

Program: To write a Verilog code for a 2:4 Decoder in Behavioral modeling using a case statement. It follows the truth table.

module dec24_beh(
output reg [3:0] y,
input [1:0] a,
input en);
always @(*)
if(en) /* only if en = 1, case statement will execute */
case(a)
0: y = 4’b0001;
1: y = 4’b0010;
2: y = 4’b0100;
3: y = 4’b1000;
default: y = 0;
endcase
else y = 0; /* if en = 0, all bits of y will remain zero */
endmodule

Like this, depending on the size of decoder, the number of statements in the case will increase along with the bit sizes of ports.

Program: To write a Verilog code for 3:8 Decoder in Behavioral modeling without using a case statement.This type of programming for hardware is NOT recommended, even if it is giving correct output.

module dec38_beh(
output reg [7:0] y,
input [2:0] a,
input en);
always @(*)
if(en) begin

y = 8’b0; /* First make all bits of y = 0 */
y[a] = 1; end /* Then make the particular bit “1”. If a = 0, zeroth bit will become “1” i.e., y[0] = 1; and if a = 5, y[5] = 1; */
else y = 0;
endmodule

This type of modeling will give correct output.

However, it is not correct when comes to the synthesis of Hardware.

This will create unnecessary latches and hardware during synthesis.

This program can be used to create any size decoder like 4:16 or 5:32 and even higher.

We need to change the port bit sizes.

Now we’ll create bigger decoders using smaller ones in Structural modeling.

Program: To write a Verilog code for 4:16 Decoder using five 2:4 decoders.

module dec4x16_str(
output [15:0] y,
input [3:0] a,
input en
);
wire [3:0] w;
dec2x4_str u0(w, a[3:2], en);
dec2x4_str u1(y[3:0], a[1:0], w[0]);
dec2x4_str u2(y[7:4], a[1:0], w[1]);
dec2x4_str u3(y[11:8], a[1:0], w[2]);
dec2x4_str u4(y[15:12], a[1:0], w[3]);
endmodule

Program: Combinational Circuit Design using Decoders

A decoder provides 2^n minterms of n input variables. Since any Boolean Function can be expressed in the sum of minterms form, a decoder that generates the minterms of the function, together with an OR gate that forms their logical sum, provides a hardware implementation of the function.

Lets take an example of a Full Adder. From the truth table of Full Adder, the sum of minterm functions are

S(x,y,z)=∑(1,2,4,7)

C(x,y,z)=∑(3,5,6,7)

So the Verilog code is

CODE:

module DEC(
input [2:0] in,
output sum,carry,
output reg [7:0] op);
always @(in)
case(in)
3’b000: op=8’b00000001;   //Decoder Truth Table
3’b001: op=8’b00000010;
3’b010: op=8’b00000100;
3’b011: op=8’b00001000;
3’b100: op=8’b00010000;
3’b101: op=8’b00100000;
3’b110: op=8’b01000000;
3’b111: op=8’b10000000;
endcase

or (sum,op[1],op[2],op[4],op[7]);   // SUM OF THE FULL ADDER: OR of the                                                                                          //minterms(1,2,4,7), GATE LEVEL MODELING
or (carry,op[3],op[5],op[6],op[7]);  //CARRY OF THE FULL ADDER // GATE LEVEL                                                                                 //MODELING, minterms(3,5,6,7)

endmodule

RTL SCHEMATIC:

TESTBENCH:

initial begininitial begin // Initialize Inputs

in = 3’b001;
// Wait 100 ns for global reset to finish

#100; in = 3’b011;
// Wait 100 ns for global reset to finish

#100; in = 3’b101;
// Wait 100 ns for global reset to finish

#100; in = 3’b111;
// Wait 100 ns for global reset to finish

#100; end      endmodule

OUTPUT:

So, if we only have decoders and OR gates, any combinational circuit can be designed using the above method.

QUIZ: With a single decoder, how many functions can be designed?

a) 1

b) 2

c) 3

4) As many as possible

Content Created: 07/07/2017