Before going to Gate-level modelling, please go through the brief description of different modelling styles here: Verilog HDL: Different types of Modelling
Gate Level Modelling
In Gate level modelling, we use primitive gates to model a circuit depending on its schematic diagram. This is part – 1 of tutorial on Structural modelling.
The different type of gates that are used in Verilog are:
These gates can have ‘n’ inputs, and one output. The truth tables of the above gates are given below. In these, the unknown value “x” and floating (or high impedance) value “z” is also included…
Usage of these Gates: Instantiation Syntax
and (out, in1, in2, in3,….); // an and gate
or (y, a, b, c, d); // a 4-input or gate
In the above representation, the first variable inside the parenthesis (in this case “y”) is output, and all the next variables (a, b, c, d, etc…) are inputs. We can have any number of inputs.
This is called instantiation of gates. The above type of instantiation is particularly called as unnamed instantiation.
We can have named instantiation also like shown below:
nand n1 (y, a, b, c); /* n1 is the name of the gate instance. It is the name you give for your convenience. This is called named instance. */
xor x1 (y, a, b, c, d, e); /* like this any name we can give, but an instance should have a unique name, two instances shouldn’t have same name. */
Now we see one input gates:
not (out, in);
buf (y, a); // y is name of output wire, a is input wire
Now tri-state buffers:
- bufif0 // acts as buffer, if control signal is zero
- notif0 // acts as not gate, if control signal is zero
bufif1 bf1 (out, in, ctrl); // Same syntax for all others
One more thing…
While doing gate level modelling, we need to connect the gates. We do it by wires, isn’t it? Here in Verilog also we connect by using wires.
These are simple wires, which we can use to connect any gate or module with.
wire n1; // this will create a single wire named n1
wire n1, n2; // this will create two single wires named n1, n2
wire [2:0] w; /* this will create a bus named containing 3 wires each named as w,w,w respectively */
We can access a single wire from a bus like shown below:
w will select zeroth line of bus w,
Similarly, w, w will select 1st and 2nd lines of bus w mentioned above.
Example to illustrate the gate level modelling:
In the above circuit
a, b, c, d are the inputs;
y is output;
w1, w2, w3 are wires that connect the gates.
w1 is output to xor gate x1,
and input to and gates a1 and a2.
Similarly w2, w3…
Verilog Program: with module name example
The above circuit is described in Verilog HDL like this in Gate level modelling.
module example (
output y, /* output port declaration */
input a, b, c, d); /* input port declaration */
wire w1, w2, w3; /* internal wires declaration */
xor x1 (w1, b, c); /* gate instantiation */
and a1 (w2, a, w1);
and a2 (w3, d, w1);
or o1 (y, w2, w3);
Please stay tuned for Advanced gate-level and switch level modelling…
Get into Structural Modelling Part-2 here:….To be updated soon…...
Content Created: 25/07/2017