VHDL is an acronym for Very high speed integrated circuit (VHSIC) Hardware Description Language which is a programming language that describes a logic circuit by the following:-
(ii) data flow behavior
(iii) and/or structure
This hardware description is used to configure a programmable logic device (PLD), such as a field programmable gate array (FPGA), with a custom logic design. The general format of a VHDL program is conceptualises BLOCKS which are the basic building units of a VHDL design. The logic circuit of a function can be described within these design blocks.
A VHDL design begins with an ENTITY block that describes the interface for the design. The interface defines the input and output logic signals of the circuit being designed.
The ARCHITECTURE block describes the internal operation of the design. Within these blocks are numerous other functional blocks used to build the design elements of the logic circuit being created.
Once the design is created, it can be simulated and synthesized to check its logical operation. SIMULATION is a framework test to see if the basic logic works according to design and concept.
SYNTHESIS allows timing factors and other influences of actual field programmable gate array (FPGA) devices to effect the simulation. It checks the design thoroughly before downloading to FPGA device.