These are the basic VHDL building blocks that are used in almost every description.
■ Entity : All designs are expressed in terms of entities. An entity is the most fundamental building block in a design.
■ Architecture : All entities which can be simulated have an architecture description. An architecture describes the behavior of the entity.
■ Configuration : A configuration statement is used to bind a component instance to an entity – architecture pair.
■ Package : A package is a collection of commonly used data types and subprograms used in a design.
Which building block of VHDL describes the behavior of entity?
Bus : The term “bus” denotes signals or a particular method of communication used in the design of hardware.
■ Attribute : An attribute is data that are attached to VHDL objects or predefined data about VHDL objects.
■ Generic : A generic is VHDL’s term for a parameter that passes information to an entity.
■ Process : A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.
■ Driver : This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers.
Which is the unit of execution in VHDL?
(d) None of the above
I’m attaching the reference textbook in the link below.
click on vhdltextbook