A VHDL entity specifies the name of the entity, the ports of the entity, and entity-related information. All designs are created using one or more entities.
Let’s take a look at a simple entity example:
ENTITY mux IS
// start of an entity statement ; name of the entity is mux.
//STANDARD package are shown in ALL CAPITAL letters
PORT ( a, b, c, d : IN BIT; // four data input ports (a, b, c, d) are of type BIT
s0, s1 : IN BIT; //two multiplexer select inputs, s0 and s1, are also of type BIT
x, : OUT BIT); // output port is of type BIT
The entity describes the following:-
(i) interface to the outside world.
(ii) It specifies
(iii) the number of ports
(iv) the direction of the ports
(v) the type of the ports
- Why ENTITY is used in the CAPITAL LETTERS?
(a) It is a STANDARD PACKAGE
(b) It is a Keyword
(c) It is a Type
(d) It is a Keyword in STANDARD PACKAGE