Yogendra cracks up NXP Interview with the Rapid Fire

Yogendra

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1. Setup and hold.

2. How to rectify them.

3. Questions related to waveform.

4. System Verilog environment-about packets, scoreboards, monitor.

5. Region in Verilog.

6. Some blocking non blocking question

7. Multicycle path ,false path.

8. Explain projects in detail.

9. Vlsi design flow.

10. What is formal verification

11. Code coverage

12. What did you do in coverage class

13. Explain cross points.

14. Difference between C, Verilog and SV.

15. Design a ckt for given waveform

16. Clock gating

17. Do you know how to write scripts

18. Few design questions based on the given waveform

19. What is FIFO? Where is it used?

20. Do you know anything about Clock domain crossing?

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