4 BIT MAGNITUDE COMPARATOR DESIGN USING VHDL.

The comparison of 2 numbers is an operation that determines whether one number is greater than, less than, or equal to the given number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The outcome of the comparison is specified by 3 binary variables that indicate whether A>B, A=B, A<B.

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Here is the VHDL code for a 4 bit comparator –

CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp is                                       –Entity of the program defines the input and the                                                                            –output variables

port ( p,q : in std_logic_vector (3 downto 0);         — p and q are input vectors of size 4

p_gt_q, p_eq_q, p_lt_q : out std_logic);

end comp;

— Architecture of a program defines the functions it perform.

Architectural Behaviour of comp is

begin

p_gt_q <= ‘0’when p>q else ‘1’;             –if p>q, then p_gt_q=0 and rest all are 1

p_eq_q <= ‘0’when p=q else ‘1’;

p_lt_q <= ‘0’when p<q else ‘1’;

end Behavioral;

1.Entity declaration:  It names the code’s inputs and outputs and defines the type of information they carry. It provides all the information needed to physically connect the design entity to the outside world or to connect it as a component in a larger system.

2.Architecture definition: It defines either the behaviour or structure of a design entity: how it accomplishes its function or how it is constructed.

In the above described program, ‘a’ and ‘b’ are the input values of 4 bit each. There are 3 output values whose values will be 0 depending on which is greater than, equal to or less than.

RTL SCHEMATIC:

vhdlrtl1

vhdlrtl2

Consider the test bench given below and the ouput for the above code.

BEGIN

— Instantiate the Unit Under Test (UUT)

uut: comp PORT MAP(

p => p,

q => q,

p_gt_q => p_gt_q,

p_eq_q => p_eq_q,

p_lt_q => p_lt_q

);

tb : PROCESS

BEGIN

p <= “1001”;

q <= “0011”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “1001”;

q <= “1001”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0001”;

q <= “0011”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “1001”;

q <= “0001”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

— Place stimulus here

wait; — will wait forever

END PROCESS;

END;

op2

For the first example p is greater than q, so the p_gt_q is 0 and rest all are 1. Similarly, the same follows for the other examples.

There’s a question for you now. How to design a comparator using data flow modeling? We will solve the above question in the next blog. Till then, keep coding. 😊

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