Multiplexer Design in VERILOG in 3 Different Ways

In this blog, I will be explaining how to design a multiplexer in VERILOG in different ways using XILINX ISE and RTL schematic. The advantage of VERILOG is that it is very flexible, in the sense that a single circuit can be designed in different ways.

A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection is controlled by a set of selection lines. Normally there are 2^n input lines and 1 output line with n selection lines. Consider the following 2:1 mux.

download[1]

In the above multiplexer, the value of the output will be I0 when sel=0 and out=I1 when sel=1.

Now consider a 4:1 Multiplexer as shown below with the corresponding truth table.

images[1]

And the equation is

exp11

Now we will design a 4:1 multiplexer in Verilog using

  • GATE LEVEL MODELING

Gate level modeling describes a circuit by specifying its gates and how they are connected to each other. In this type of coding, first the output variable is written and after that input variables are written. The Verilog code for the 4:1 mux using gate level modeling will be

CODE:

// GATE LEVEL MODELING

module gatelevel(i0,i1,i2,i3,s0,s1,y);

input i0,i1,i2,i3,s0,s1;

output y;

wire a,b,c,d,e,f;        // for partial outputs

not (a,s0);                  // a=~s0

not (b,s1);

and (c,i0,a,b);            // c=i0&&a&&b

and (d,i1,s0,b);

and (e,i2,a,s1);

and (f,i3,s0,s1);

or (y,c,d,e,f);          // y=c||d||e||f

endmodule
So in this code, we used the predefined gates and designed the multiplexer using wires. WIRE keyword is used in order to connect the input with the partial outputs and connecting partial outputs with the ouput

RTL Schematic

rtl1

  • DATA FLOW MODELING

In this technique, operators that act on binary operands to produce a binary result are used. There are about 30 operators in VERILOG HDL which includes &&, ||, ! etc.

CODE:

module dataflow(i0,i1,i2,i3,s0,s1,y);

input i0,i1,i2,i3,s0,s1;

output y;

assign y=(!s0&&!s1&&i0)||(s0&&!s1&&i0)||(!s0&&s1&&i2)||(s0&&s1&&i3);

endmodule

In this modeling, direct equations can be written in order to execute the system.

RTL Schematic

rtl1

Thus, there is no such difference in gate level modeling and data flow modeling when it comes to the RTL schematic even though the style of the coding is completely different.

  • BEHAVIORAL MODELING

This modeling technique represents digital circuits at a functional level. It is used mostly to describe sequential circuits but we can use it to design a combinational circuit. It uses the keyword always, followed by an optional event control expression and a list of procedural assignment statements. The case keyword is similar to the switch operator in C language and it checks for the value and the corresponding statement executes.

CODE:

module behavioral(

input i0,i1,i2,i3,

output reg y,

input[1:0] sel

);

always @ (i0,i1,i2,i3,sel)   // Mention all the inputs inside the always block

case(sel)

2’b00: y=i0;            // Follow the truth table

2’b01: y=i1;

2’b10: y=i2;

2’b11: y=i3;

endcase

endmodule

always block is used in order to make sure that whenever the values inside the block changes, the entire body following always block executes.  The keyword reg used here is the same as the wire which was used in data flow modeling. Contrary to the wire data type, a reg data type retain its value until a new value is assigned.

RTL schematic

rtl2

TESTBENCH [ FOR ALL THE ABOVE CODES ]:

initial begin

// Initialize Inputs

i0 = 1;

i1 = 0;

i2 = 0;

i3 = 0;

sel = 2’b00;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

i0 = 0;

i1 = 1;

i2 = 0;

i3 = 0;

sel = 2’b01;

// Wait 100 ns for global reset to finish

#100;

i0 = 0;

i1 = 0;

i2 = 1;

i3 = 0;

sel = 2’b10;

// Wait 100 ns for global reset to finish

#100;

i0 = 0;

i1 = 0;

i2 = 0;

i3 = 0;

sel = 2’b11;

// Wait 100 ns for global reset to finish

#100

end

endmodule

OUTPUT:

op

OUTPUT VERIFICATION :

When s0=0 and s1=0, y=i0=1

When s0=1 and s1=0, y=i0=1

When s0=0 and s1=1, y=i0=1

When s0=1 and s1=1, y=i0=0

So as we can see, the multiplexer output will be the same no matter what modeling we use in order to get the result. For a given circuit you can use any model which you find easy to use and proceed with it. Mostly behavioral modeling is preferred because it is used in sequential circuits too.

So I end my today’s blog with a question. Can we design an AND gate using a 2:1 multiplexer?  If yes, then how? And how to design it in VERILOG? I will tell you the solution in the next blog. Till then keep coding.

Any questions? Feel free to ask me at niteshm815@gmail.com

 

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

Powered by WordPress.com.

Up ↑

%d bloggers like this: