In this blog post, we will be learning about logical and arithmetic operators using a system design approach in VHDL. An Arithmetic and Logic Unit is a digital circuit which performs arithmetic, logical and shift operations. It is the fundamental building block of central processing unit (CPU).

Let us design a simple ALU using some arithmetic and logical operators. The behavioural modeling in VHDL is same as VERILOG, except the keyword ‘*always’ *is replaced by the keyword ‘*process’.* One input will be used in order to determine which operation to perform. If input =0, then addition will be performed, if input =1, then subtraction etc. + and – operators are used for addition and subtraction. Logical operators are used with the keyword “and”, “or”, “xor” etc. Let’s see the code.

**CODE:**

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

— ALU OPERATION

entity alu is

port ( p,q : in std_logic_vector (3 downto 0); –p and q are the input lines

r : in std_logic_vector (2 downto 0); — r is the selection line

result : out std_logic_vector (3 downto 0)); — result is the output

end alu;

architecture Behavioral of alu is

begin

process(p,q,r) — same like always block in verilog (behavioral modeling)

begin

case r is

when “000” => result <= p+q; — when r=0, result=p+q

when “001” => result <= p-q; — when r=1, result=p-q

when “010” => result <= p and q; — when r=2, result=p and q

when “011” => result <= p or q; — when r=3, result=p or q

when “100” => result <= p xor q; — when r=4, result=p xor q

when “101” => result <= p nor q; — when r=5, result=p nor q

when “110” => result <= p nand q; — when r=6, result=p nand q

when “111” => result <= not p; — when r=7, result= not p

when others => result <= “0000”;

end case ;

end process;

end Behavioral;

Therefore, the output result value will be an operation between p and q depending on ‘r’ value. For example, if r=6, then the output will be the NAND operation of p and q.

**RTL SCHEMATI****C**

**TEST BENCH:**

tb : PROCESS

BEGIN

p <= “0100”;

q <= “0011”;

r <= “000”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “001”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “010”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “011”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “100”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “101”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “110”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

p <= “0100”;

q <= “0011”;

r <= “111”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

wait; — will wait forever

END PROCESS;

END;

**OUTPUT:**

Therefore, as we can see, the output is a binary operation between the two input operators depending on the r input value.

**QUIZ**:

A. Using which logical operator given below, we can design a parity generator?

- AND
- OR
- XOR
- NAND

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