5:32 Decoder Design using 4 3:8 Decoders and 1 2:4 Decoder in VERILOG

So I asked a question in my last blog.. How to design an AND gate using 2:1 multiplexer ?Got the answer? If not, then here is the answer. Connecting the A input to the selection line will convert a 2:1 multiplexer into an AND gate. Try it and verify it using VERILOG.

So today’s topic is designing a 5:32 decoder using 4 3:8 decoders and a 2:4 decoder. Many a times, it happens that we don’t have a larger decoder, so we normally combine small decoders to design a bigger one. Let’s start with the theory behind it.

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2^n unique output lines. As an example, consider a 3:8 decoder, the three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables. The operation of the decoder will get clarified by the truth table. For each possible input combination, there are 7 outputs which are equal to 0 and only one that is equal to 1.

For example if in=111=7(decimal), the output D7 will be 1 and rest all the outputs will be 0. Similarly if in=101=5, the output D5 will be 1 and rest all outputs will 0.

cd               tt

It is mandatory that en is 1 for the output to appear. If en is 0, the output is 0 no matter what the input is.

So we have 4 3:8 decoders and 1 2:4 decoder, how to design a 5:32 from them? Since we need 32 output lines, 4 3:8 decoders will give us the 32 outputs.  The 2:4 decoder will give us 4 outputs that will be connected to the 4 3:8 decoders in the enable pin for generating the output. The input a[0],a[1] and a[2] is given to all the 3:8 decoders and depending on which 3:8 decoder’s enable pin is 1, corresponding output will be shown and rest all decoders will give 00000000 as the output ( 0 in all the 8 output lines ). The explanation will become clear from the circuit diagram.

download

In the circuit diagram, consider the input is 11111, it means that the value is 31, so the output should be 1 followed by 31 0s. Since a[3] and a[4] are 1, the 2:4 decoder will produce the output 1 on the 4th output line and 0s on the other output lines. These become enable pins for 3:8 decoders, therefore since first 3 en are 0, the output of first 3 decoders will be 000000000000000000000000. For the last decoder, since en=1 and a[0]=a[1]=a[2]=1( input = 111=7), the output will be 10000000( D7=1 rest all 0). And finally we will get the final answer as 1 followed by 31 0s.

CODE:

// Design of the above 5:32 decoder circuit using 4 3:8 and 1 2:4 decoder

module decoder5x32(

input [4:0] a,                                 // 5 input lines

input en,                                       // enable pin

output [31:0] y );                        // 32 output lines

wire [3:0] w;                                //for storing the output of 2:4 decoder

decoder2x4 x1(w,a[4:3],en);     // Calling 2:4 decoder with en and a[4:3] as inputs and w as                                                          //output

decoder3x8 x2(y[7:0], a[2:0],w[0]);  // Calling 3:8 decoder with[0] as enable

decoder3x8 x3(y[15:8], a[2:0],w[1]);

decoder3x8 x4(y[23:16], a[2:0],w[2]);

decoder3x8 x5(y[31:24], a[2:0],w[3]);

endmodule

//2:4 decoder

module decoder2x4(

output reg [3:0] y,

input [1:0] a,

input en);

always @(a,en)               // behavioral modeling, give all the inputs inside always block

if(en)

case(a)

2’b00: y=4’b0001;    // Use the truth table. Very easy to code in behavioral modeling.

2’b01: y=4’b0010;

2’b10: y=4’b0100;

2’b11: y=4’b1000;

default: y=0;

endcase

else y=0;              //if en=0, the output should be 0

endmodule

// 3:8 decoder

module decoder3x8(

output reg [7:0] y,

input [2:0] a,

input en);

always @(a,en)

if(en)

case(a)                                  // Use truth table of 3:8 decoder

0: y =8’b00000001;           // if input is 000=0

1: y =8’b00000010;           // if input is 001=1

2: y =8’b00000100;

3: y =8’b00001000;

4: y =8’b00010000;

5: y =8’b00100000;

6: y =8’b01000000;

7: y =8’b10000000;

default: y=0;

endcase

else y=0;        // if en=0, y=0

endmodule

RTL Schematic

rtl1

rtl2

TEST BENCH

initial begin

                                // Initialize Inputs

                                a = 5’b01010;

                                en = 1;

                                // Wait 100 ns for global reset to finish

                                #500;

                                // Add stimulus here

a = 5’b11111;

                                en = 1;

                                // Wait 100 ns for global reset to finish

                                #100;

                end

endmodule

OUTPUT:

op

VERIFICATION:

If input is 01010=10 the 11th bit should be 1

If input is 11111=31, the 32nd bit should be 1

So here is a question for today.. How to design any combinational circuit with a decoder? We will design this in the next blog. Till then, keep coding 🙂

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