So today we will see an application of XOR Gate, which is parity generation. A parity bit is used for the purpose of detecting errors during the transmission of binary information. A parity bit is an extra bit included with the binary message to make the number of ones either even or odd. An error is detected if the checked parity doesn’t correspond with the one transmitted.

The circuit that generates the parity bit is called parity generator. So with this explanation, let us design an even  parity generator. Here is the truth table of an even parity generator.

INPUTS                                                                                             OUTPUT

 x y z Parity Bit 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1

As seen from the truth table, in this even parity generator,  if the number of 1’s in the input are odd, the output is 1 making the total numbers of ‘1’ be even.  If the number of 1’s in input is even, the output is 0 since the number of input ‘1’ is already even.  By closely observing the truth table, it can be understood that the output is a mere XOR of input bits.

The three bits in the message, together with the parity bit are transmitted to their destination, where they are applied to a parity checker circuit to check for possible errors.

VERILOG CODE:

module parity(

input x,y,z,

output result);

xor (result,x,y,z);  // SIMPLE XOR OPERATION : Gate Level Modeling

endmodule

TEST BENCH:

initial begin

// Initialize Inputs

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

RTL SCHEMATIC

OUTPUT:

The output can be verified through truth table and it can be sent along with the message bits to the receiver where the receiver will check whether the message is corrupted or not.

QUIZ: How the receiver will determine that the message received is error free ? We will see the solution in our next blog. Till then, keep coding 🙂