RAM Design using VERILOG

So today, we will design a memory unit which is RAM, Random Access Memory. A memory unit is a device to which binary information is transferred for storage and from which information is retrieved for processing. RAM stores new information for later use. It can perform both read and write operations.

ram2.PNG

ram6

RAM consists of data input and output lines, address selection lines, and control lines that specify the direction of transfer. The n data input lines provide the information to be stored in the memory and n output lines supply the information coming out of the memory. The k address lines specify the particular word chosen among many. There are two control lines. Memory enable should be 1 for the input/output operations to take place and the READ/WRITE should be 1/0 for either reading or writing operations to take place.

In VERILOG, memory is designed as an array of registers using a reg keyword. The first number in the array specifies the number of bits in a word and the second gives the number of words in the memory. For example a memory of 1024 words with 16 bits per word is given as

reg[15:0] memory[0:1023]

This statement describes a 2-dimensional array named memory of 1024 registers, each containing 16 bits.

So the VERILOG code is..

module RAM(en,rw,adr,datain,dataout);
input en,rw;                                 // CONTROL LINES
input [3:0]datain;                       // INPUT DATA LINES
input [5:0]adr;                            // ADDRESS LINES
output reg [3:0]dataout;           // OUTPUT DATA LINES
reg[3:0] mem[0:63];                  // 64X4 MEMORY
always @(en or rw)
if(en)
if(rw)                                           // IF rw=1, READ
dataout <= mem[adr];             // Take data from the memory and assign it to the o/p lines
else
mem[adr] <= datain;               // IF rw=0, WRITE data into the memory
else
dataout <=4’bz;                        // HIGH IMPEDANCE STATE
endmodule

The datain and dataout lines have 4 bits each. The input adr must have 6 bits ( since 2^6=64) and the number of bits in each word is determined by the data line size, which is 4 bits. So the memory size is 64 rows with 4 bits in each row.

RTL SCHEMATIC:

ram2.PNG

ram3.PNG

So the first schematic represents the black box of the RAM which specifies the input and the output lines. The second schematic shows the internal configuration in terms of registers and the wires connecting them. As seen from the RTL schematic, it is seen that in order to design this complex memory unit, very easy coding is incorporated. 🙂

TESTBENCH:

initial begin

// Initialize Inputs

en = 1;

rw = 0;

adr = 6’b000001;

datain = 4’b1010;

// Wait 100 ns for global reset to finish

#500;

// Add stimulus here

en = 1;

rw = 1;

adr = 6’b000001;

// Wait 100 ns for global reset to finish

#500;

end

endmodule

OUTPUT:

ram1.PNG

And the output is self understanding. First rw is 0, and the datain 1010 is stored in the memory address 000001. After 500ns, rw becomes 1 and the read operations take the value from 000001 and put it in dataout.

 

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