Implementation of 8 input AND in VHDL using LOOPS

A loop statement contains a sequence of sequential statements that can be repeatedly executed, zero or more times. Consider the iteration scheme of a for loop

for identifier in range loop

 sequence of statements

end loop;

In a ‘for’ loop, the identifier keyword ‘for’ serves as an implicit declaration of a loop parameter with the specified name.

So, the problem statement is the design of a system that is 8 input AND which should be implemented by repeatedly iterating the two operand VHDL, AND operator.

Here the logic is, if one of the inputs is 0, the output will be 0. So, in the beginning, the output is set as 1 by default. The ‘for’ loop checks for the input bit to be 0. The moment input bit 0 is identified, the output is assigned 0. If during all the bits traversal, all the inputs are 1, then the output is also 1.

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder is

port ( inp: in std_logic_vector (7 downto 0);   — 8 bit input

op: out std_logic);

end adder;

architecture Behavioral of adder is

begin

process(inp)     –BEHAVIORAL MODELING

begin

op <=’1′;     –Default op is initialised with 1

for i in 7 downto 0 loop –for loop syntax

if inp(i)=’0′ then   –when ip=0, op is 0

op <=’0′;

end if;

end loop;

end process;

end Behavioral;

RTL SCHEMATIC:

TEST BENCH:

BEGIN

— Instantiate the Unit Under Test (UUT)

uut: adder PORT MAP(

inp => inp,

op => op

);

tb : PROCESS

BEGIN

inp <=”11111111″;

— Wait 100 ns for global reset to finish

wait for 100 ns;

— Place stimulus here

inp<=”11100011″;

— Wait 100 ns for global reset to finish

wait for 100 ns;

wait; — will wait forever

END PROCESS;

END;

OUTPUT: