4 bit Ripple Adder using VERILOG

Digital computers perform a variety of information processing tasks. Among the functions encountered are the various arithmetic operations. The most basic arithmetic operation is addition of two binary digits.

4-bit-adder.jpg

Addition of n bit numbers require a chain of n full adders with each output carry connected to the input carry of the next higher order full adder. So we will design it in the VERILOG as

VERILOG CODE:

module full_adder (output S,C, input x,y,z);   //FULL ADDER 

 assign S = ((x^y)^z);         //sum is the XOR of x,y and z

 assign C= (x&&y)||(y&&z)||(x&&z);  //Carry operation

endmodule

//STRUCTURAL MODELING

module ripple( output [3:0] sum, output C4, input [3:0] A,B,input C0);

wire C1,C2,C3;

full_adder FA0(sum[0],C1,A[0],B[0],C0);  // 1st Full Adder

full_adder FA1(sum[1],C2,A[1],B[1],C1);  // 2nd Full Adder

full_adder FA2(sum[2],C3,A[2],B[2],C2);  // 3rd Full Adder

full_adder FA3(sum[3],C4,A[3],B[3],C3);  // 4th Full Adder

endmodule

RTL SCHEMATIC

1.PNG

2

3

4

TEST BENCH

initial begin

                                // Initialize Inputs

                                A = 4’b1010;

                                B = 4’b0101;

                                C0 = 0;

                                // Wait 100 ns for global reset to finish

                                #100;

                                // Add stimulus here

                                A = 4’b1010;

                                B = 4’b1101;

                                C0 = 0;

                                // Wait 100 ns for global reset to finish

                                #100;

                end

endmodule

OUTPUT:

6

DELAY REPORT:

7

As seen from the delay report, the logic delay is 7.540 ns which is more than the Carry Lookahead Generator. Therefore this kind of adder is practically not used much nowadays.

 

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