Implementation of a Combinational System to Determine the Number of 1s in the Input Vector using LOOPS in VHDL.

As we saw the loops concept yesterday, today we will implement another digital system which will determine the number of 1s in the input vector using for loop and outputs the binary representation of this number as the value count. The architecture must describe a combinational circuit and not the sequential one.

Before we start with the programming of the code, we should understand that in this problem statement, we need to have a variable which will increase by itself whenever ‘1’ is identified in the input pattern. There are four kinds of VHDL objects namely variables, signals, constants and files.

There are two kinds of variables: Normal variables and Shared variables. Shared variables can be accessed by multiple processes whereas a normal variable can be only accessed by a single process and are synthesizable.

DECLARATION OF A VARIABLE:

variable identifier: type range

In the above declaration, the identifier is the name of the variable. The type of the variable defines whether it is standard logic vector or an unsigned value. Variables are assigned using := operator.

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ones_count is

port (inputs : in std_logic_vector (3 downto 0);  –input vector

count : out std_logic_vector (1 downto 0)    –output vector to store no of 1s

);

end ones_count;

architecture Behavioral of ones_count is

begin

process(inputs)   –BEHAVIORAL MODELING

variable x : unsigned (1 downto 0);    –Declaration of the variable

begin

x :=”00″;          –Initialising x with 0

for i in 3 downto 0 loop    –FOR LOOP to check no of 1s

if (inputs(i)=’1′) then       –if input(i) is 1, increment x

x := x+’1′;

end if;

end loop;

count <= std_logic_vector(x);   –Convert the unsigned value into standard 

–vector since the op should be in binary value 

end process;

end Behavioral;

So, in the above code, an unsigned variable x is declared and there’s an increment whenever a ‘1’ is detected in the input signal using combinational logic. Finally, the unsigned value x is converted into standard logic vector and assigned to count.

RTL SCHEMATIC:

one1

one2.PNG

TEST BENCH:

BEGIN

inputs <= “0110”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

inputs <= “0010”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

wait; — will wait forever

END PROCESS;

END;

OUTPUT:

out3

So, as verified from the simulation, this combinational system can be used in order to calculate the number of 1s in the input pattern.

 

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