So today we will design a combinational system which will incorporate loops concept. The problem statement is

A combinational circuit takes as its inputs the votes from three judges and computes the winner of the competition. Each judge has two switches, one for contestant A and one for another contestant B. Each judge must assign a 1 to one contestant and 0 to the other. We have to design a combinational system which computes the winner by counting the number of ones and comparing them. So let’s see the code

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.numeric_std.all;

entity mini is

port (scoresA, scoresB : in std_logic_vector (2 downto 0);

winner : out std_logic_vector (1 downto 0)

);

end mini;

architecture Behavioral of mini is

begin

process(scoresA,scoresB)

variable x : unsigned (1 downto 0);

variable y : unsigned (1 downto 0);

begin

x :=”00″;

y :=”00″;

for i in 2 downto 0 loop

if scoresA(i)=’1′ then   –COUNT THE NO OF 1s FOR A

x := (x+’1′);

if (scoresB(i)=’1′) then  –COUNT THE NO OF 1s FOR B

y :=  y+’1′;

end if;

end if;

end loop;

if(x=0 and y=0) then

winner <= “00”;   — NO DECISION

end if;

if(x>y) then

winner <= “01”;— if x>y, then x is the winner and output 01 is shown

else if (x<y) then

winner <= “10”;  — if x<y, then y is the winner and output 10 is shown

end if;

end if;

end process;

end Behavioral;

RTL SCHEMATIC:

TEST BENCH:

BEGIN

scoresA <= “101”;

scoresB <= “010”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

– Place stimulus here

scoresA <= “000”;

scoresB <= “000”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

scoresA <= “001”;

scoresB <= “110”;

— Wait 100 ns for global reset to finish

wait for 100 ns;

wait; — will wait forever

END PROCESS;

END;

OUTPUT:

So, the looping concept is very important in combinational design circuit with which we can associate it to the sequential circuit without even having latches or flip flops and all those timing constraints which comes with the sequential circuits