An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2^n inputs and n outputs. The output lines generate the binary code corresponding to the input value. Consider the 8:3 encoder shown below with the truth table.

From the truth table, the expressions for the outputs can be expressed as

Z=D1+D3+D5+D7

Y=D2+D3+D6+D7

X=D4+D5+D6+D7

Therefore the encoder can be implemented with the help of OR gates.

And the Verilog implementation is given below:

VERILOG CODE:

module encoder(

input [7:0] inp,

output reg [2:0] op);

always @( inp)   //BEHAVIORAL MODELING

case(inp)

8’b10000000: op <= 3’b000;

8’b01000000: op <= 3’b001;

8’b00100000: op <= 3’b010;

8’b00010000: op <= 3’b011;

8’b00001000: op <= 3’b100;

8’b00000100: op <= 3’b101;

8’b00000010: op <= 3’b110;

8’b00000001: op <= 3’b111;

endcase

endmodule

WHY NORMAL ENCODER FAILS ?

The encoder has the limitation of only one input being 1 at a given time. If 2 inputs are active simultaneously, the output produces an undefined combination. For example if D3 and D6 are 1 simultaneously, the output of the encoder will be 111 because all 3 outputs are equal to 1. But the output 111 does not represent either 3 or 6. It represents D7. To resolve this ambiguity, priority encoders are used widely to ensure that only one input is encoded. The priority encoder will be seen in the next part of the blog.

RTL SCHEMATIC

VERILOG TESTBENCH

initial begin

// Initialize Inputs

inp = 8’b10000000;

// Wait 100 ns for global reset to finish

#100;

inp = 8’b00010000;

// Wait 100 ns for global reset to finish

#100;

inp = 8’b00000001;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

OUTPUT:

QUIZ:

1. Which among the following uses encoder  ?