PRIORITY ENCODER IN VERILOG

A priority encoder is an encoder circuit that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to at the same time, the input having the highest priority will take precedence. Consider the 4:2 Priority encoder below. Input D3 has the highest precedence, in the sense, if D3 is 1, the output will be 11 no matter what the other input bits are.

                         INPUT                                                                                   OUTPUT

D0 D1 D2 D3 X Y
1 0 0 0 0 0
x 1 0 0 0 1
x x 1 0 1 0
x x x 1 1 1

The maps for the simplifying outputs x and y are shown below

x=D2+D3

y=D3+(D1.D2′)

y3

y4.PNG

VERILOG CODE:

module encoder(

input [3:0] inp,

output [1:0] op);

assign op[1]=inp[2]||inp[3];   // USING THE ABOVE EQUATIONS

assign op[0]=inp[3]||(inp[1]&&(!inp[2]));

endmodule

VERILOG TEST BENCH

initial begin

                                // Initialize Inputs

                                inp = 1;

                                // Wait 100 ns for global reset to finish

                                #100;

                                  inp = 3;

                                // Wait 100 ns for global reset to finish

                                #100;

                                  inp = 7;

                                // Wait 100 ns for global reset to finish

                                #100;

                                  inp = 15;

                                // Wait 100 ns for global reset to finish

                                #100;

                end

endmodule

OUTPUT:

y2

So as we can see from the output simulation, when d[3] is 1, the output will be 11 no matter what is the value of d[0],d[1] or d[2].

Therefore, priority encoders prove to be a better solution as compared to normal encoders when the encoding is required for sophisticated use where all the input combinations can be implemented.

QUIZ

For the 4:2 priority encoder with D0 as highest prioirty and D3 lowest priority, what will be the expressions for the output bits ?

 

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