A BCD to SEVEN SEGMENT DECODER is a combinational circuit that converts a decimal digit in BCD to  an appropriate code for the selection of segments in an indicator used to display the decimal digits in a familiar form. The seven outputs of the decoder select the corresponding segments in the display. There are actually two kinds of seven segment display, cathode connected and anode connected. In cathode connected seven segment display, the segments which we want to glow becomes 1. In anode connected, those become 0 and rest all segments become 1.

Consider the seven segment display shown below with the circuit diagram.

The truth table for the seven segment display is

INPUT                                                         OUTPUT

 A B C D a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1

So we got the TRUTH TABLE for the cathode connected seven segment display. Now the only thing is to code. And you all know how to code once you get the truth table. So here we go…

VERILOG CODE:

module sevseg(

input [3:0] inp,

output reg [6:0] op);

always @(inp)

case(inp)

4’b0000: op <=7’b1111110;

4’b0001: op <=7’b0110000;

4’b0010: op <=7’b1101101;

4’b0011: op <=7’b1111001;

4’b0100: op <=7’b0110011;

4’b0101: op <=7’b1011011;

4’b0110: op <=7’b1011111;

4’b0111: op <=7’b1110000;

4’b1000: op <=7’b1111111;

4’b1001: op <=7’b1110011;

endcase

endmodule

RTL SCHEMATIC

TESTBENCH

initial begin

// Initialize Inputs

inp = 0;

// Wait 100 ns for global reset to finish

#100;

inp = 3;

// Wait 100 ns for global reset to finish

#100;

inp = 6;

// Wait 100 ns for global reset to finish

#100;

inp = 9;

// Wait 100 ns for global reset to finish

#100;

end

OUTPUT

So after designing the cathode connected seven segment display, it will be very easy to design an anode connected seven segment. Try it and design it in XILINX.