Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors, etc. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest clement in the system.
Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas.
Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers.
In our project when we compare the power consumption of all the multipliers we find that serial multipliers consume more power. So where power is an important criterion there we should prefer parallel multipliers like booth multipliers to serial multipliers. The low power consumption quality of booth multiplier makes it a preferred choice in designing different circuits.
In this project we have implemented Xilinx codes for various multipliers like vedic multiplier, array multiplier, and booth’s multiplier. Then we compared the working of different multipliers by comparing the power consumption by each of them. We came to know that vedic multiplier technique is less power consuming.