This project represents the reviewing of the construction of 32 bit high speed Kogge Stone Adder. High speed additions and multiplications are fundamental requirements of high performance processors. Therefore, fast and accurate operation of digital system depends upon the performance of adders. The core of every microprocessor, digital signal processor, System on chip is its data path. At the centre of these data paths are arithmetic units such as adders, comparators, and multipliers. Designing an efficient adder, the designer must optimize the parameters such as area, delay and power.

In the VLSI modern technology, delay in data path is considered to be the most crucial parameter. In this project, Kogge Stone Adder will be designed, simulated and implemented in XILINX FPGA using VERILOG HDL.

Kogge Stone Adder is the parallel prefix Adder and broadly considered as one of the fastest addition method. Carry generation is much faster due to the use of parallel circuits. The Kogge Stone Adder consists of 3 stages. In the pre-processing stage, propagation and generation signals are generated. Carry generation Stage includes several black cells and grey cells which is used to generate carry for the next stages and finally post processing. In post-processing stage, final sum and output carry is produced.



Propagation Signal: P(a,b)= A^B

Generation Signal:  G(a,b)=A.B

From the Carry Generation Stage, we get the Black cell and Grey cells. The equation for those are

Gblack = (Gprev.P)+G

Pblack = (P.Pprev)

G grey = (Gprev.P)+G

Sum and Carry out bits is generated in the post processing stage:


Kogge stone adder is one of the fastest addition techniques which increases its performance, but on the other hand, it occupies much area and wiring congestion problems.

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