SEQUENTIAL LOGIC AND SR LATCH

So we have seen a lot about combinational circuits and it’s time we move our concentration to the sequential circuits, the other part of the digital system which is used almost everywhere. The use of registers, counters, memory units such as RAM and ROM are all sequential circuits. The circuit which not only depends on its inputs but also depends on its previous outputs is called a sequential circuit.  Consider the block diagram of a sequential circuit as shown below

 

t1.gif

 

It consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing binary information.

So we will start our coding with the Synchronous Sequential Circuits, the sequential circuits in which the output changes when the clock becomes either low or high (Level Triggered), or during the negative and positive edges (Edge Triggered) of the clock.

The storage elements used in the sequential circuits are called flip flops. A flip flop is a binary storage device which is capable of storing one bit of information and controlled by a clock. However latches also store one bit of information but is not controlled by the clock.

 

So today we will see SR LATCH

The SR latch is a circuit with two cross coupled NOR gates or two cross coupled NAND gates and two inputs labelled S for set and R for reset. Consider the SR Latch using two crossed NOR. It has two useful states. When output Q=1 and Q’=0, the latch is said to be in SET state. When Q=0 and Q’=1, the latch is said to be in RESET state.

OPERATION OF SR FLIP FLOP:

Under normal conditions, both inputs of the latch remain at 0 unless the state has to be changed. The moment 1 is given to the S input, the latch goes to the set state. And when 1 is given to the R state and S state is 0, the latch goes to the reset state. If a 1 is applied to both of the inputs, both outputs go to 0. This action produces an undefined next state and it is normally avoided.

t2.png

So whenever after setting or resetting the latch, we have to store the value, we just provide 0 at both the inputs to latch the previous input to the output so that it will store the binary information.

 

VERILOG CODE:

module sr(en,s,r,q);
input en,s,r;
output reg q;
always @(en or s or r)  // behavioral modeling
begin
if(en)     // When en=1, then only perform the latch operations
begin
case({s,r})
2'b00: q <= q;      // when r=0,s=0, output=previous input
2'b01: q <= 1'b0;   // when s=0,r=1, output=0
2'b10: q <= 1'b1;   // when s=0,r=1, output=0
endcase
end
end
endmodule

 

TEST BENCH:

initial begin

                              

                                en = 0;

                                s = 0;

                                r = 0;

   #2 en=1;

                s=1;

                r=0;

                #40;

                s=0;

                r=0;

                #40;

                s=0;

                r=1;

                end
endmodule

 

OUTPUT:

T3.PNG

So we saw how the SR LATCH will be able to store a bit of information. In the next blog we will see SR FLIP FLOP along with other flip flops.

 

QUIZ: Which is better ?

  1. LATCH
  2. FLIP FLOPS

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