So yesterday I explained about the SR LATCH and its operation. The disadvantage of having an SR latch is that it has an undesirable condition when both the inputs go to 1. One way to eliminate the undesirable condition of the indeterminate state in the latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done in the D latch as shown below. Whenever input is 1, its complement will go to the other NOR gate and there will never be two 1 inputs at the same time. So according to the logic diagram, whenever enable input is 1, and the input D is 1, the output is 1 (set state), when D is 0, the output is 0.

VERILOG CODE

```module dff(en,d,q);
input en,d;
output reg q;

always @(en or d)
begin
if(en)
begin
case(d)
1'b0: q <= 1'b0;
1'b1: q <= 1'b1;
endcase

end
end
endmodule```

RTL SCHEMATIC: TEST BENCH:

```initial begin

en = 0;

d = 0;

#5; en=1;

#10; d=1;

#10; d=0;

#10; d=1;
endmodule```

OUTPUT: QUIZ: Where is D Flip Flop mostly used ?

1. REGISTERS
2. ASYNCHRONOUS CIRCUITS