EDGE TRIGGERED D FLIP FLOP

The construction of a D Flip Flop with 2 D latches and an inverter is made in order to give it an edge triggered sequential device. The first latch is called the master and the second the slave. The circuit samples the D input and changes its output only at the negative edge of the synchronizing or controlling clock. When the clock is 0, the output of the inverter is 1. The slave latch is enabled, and its output Q is equal to the master output Y. The Master latch is disabled because clock=0. Thus a change in the output of the flip flop can be triggered only by and during the transition of the clock from 1 to 0.

ff3.png

VERILOG CODE:

module dff(clk,d,q);
input clk,d;
output reg q;

always @(negedge clk)   // whenever clk goes from 1 to 0,then change the output
q <= d;

endmodule

RTL SCHEMATIC:

ff1

ff2.PNG

So as seen from the RTL Schematic, the bubble before the clock of the D flip flop determines the negative triggering (1 -> 0) and the triangle after the bubble determines edge triggering.

TESTBENCH:

initial begin

                                     

                                clk = 1'b1;

                                forever #10

                                clk=~clk;

                                end

                               

                                initial

                                begin

                                d=1'b1;

                                #15;

                                d=1'b0;

                                #20;

                                d=1'b1;

                                #15;

      end

                                endmodule

OUTPUT:

FF4

In designing sequential circuits we will see that using D flip flop is the easiest to way to design  any sequential circuit.

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