JK FLIP FLOP

Having studied about D flip flop, one may ask a question as to why to study another flip flop. Well the answer lies here. There are three operations that can be performed using flip flops: Set it to 1, reset it to 0, and complement its output. With only a single input, the D flip flop can set or reset the output, but is unable to complement the output for a specific input value. Synchronized by a clock signal, the JK Flip Flop has 2 inputs and perform all 3 operations. The J input sets the output to 1, the K input resets the output to 0, and when both the inputs are enabled, the output is complemented.

jk3.jpg

Therefore, as seen from the characteristics table, when J=K=0, the next state is equal to the previous state. When J=1 and K=0 or J=0 and K=1, the next state is the value of J. When J=K=1, the next state is the complement of the previous state.

VERILOG CODE;

module jk(clk,j,k,q);

input clk,j,k;

output reg q;


//JK FLIP FLOP

always @(posedge clk)

case ({j,k})

2'b00: q <=q;   //WHEN J=K=0, NO CHANGE

2'b10: q <=1'b1;   //WHEN J=1,K=0, THEN Q=1, SET STATE

2'b01: q <=1'b0;   //WHEN J=0,K=1, THEN Q=0, RESET STATE

2'b11: q <=!q;    //WHEN J=K=1, THEN Q= ~Q

endcase

endmodule

 

 

RTL SCHEMATIC

JK3.PNG

So as seen from the RTL SCHEMATIC, JK flip flop is actually a D flip flop with the D input as JQ’+K’Q.

TEST BENCH:

initial begin

                                clk = 1'b1;

                                forever #10

                                clk=~clk;

                                end

                               

                                initial

                                begin

                                j=1'b1;

                                k=1'b0;

                                #35;

                                j=1'b0;

                                k=1'b1;

                                #20;

                                j=1'b1;

                                k=1'b1;

                                #30;

                                j=1'b0;

                                k=1'b0;

      end

                                endmodule

 

OUTPUT:

jk4.PNG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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