The T Flip Flop is a complementing flip flop and can be obtained from a JK FLIP FLOP when J and K inputs are tied together. When T=0, a clock edge does not change the output; the output follows its previous output. However when T=1, the output will be the complement of its previous output. T flip flop is mostly used in design of binary and BCD counters as we will see in the upcoming blogs.
Therefore, as seen from the characteristic table, when T=0, output is equal to the previous output. When T=1, the current output is the complement of previous output.
The T flip flop is constructed using D flip flop and an exclusive OR gate through the equation.
D = T xor Q = T Q’ + T’ Q
module t(clk,t,res,q); input clk,t,res; output reg q; always @(posedge clk) if(!res) q <=1'b0; //for initial conditions else case(t) 1'b0 : q <= q; 1'b1 : q <= !q; endcase endmodule
initial begin //clock signal clk = 1'b1; forever #10 clk=~clk; end // input signal initial begin t=0; #55; t=1; #20; end // res signal initial begin res=0; #5; res=1; end endmodule
So can you infer something from the output ? If not here is the most important thing about T flip flop which is why it is used with microcontrollers and microprocessors. If T=1, the output frequency is exactly the half of the clock frequency. This property is used with microcontrollers and other peripherals. Various peripherals such as ADC, DAC have a clock which is very slow as compared to the microcontroller. So in order to make the clock equal, it is passed through T flip flops in order to reduce the frequency of the microcontroller.