ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS: MOORE MACHINE

We discussed MEALY MACHINE in our previous blog in which the output depends on input variables as well as the state variables. However in MOORE MACHINE, the output solely depends on state variables. Any change in input which does not make any change to the state values, will not change the output. In Digital Design, mostly MOORE Machines are used since the output will only change when the state changes: positive or negative edge of the clock.

Consider the sequential clocked circuit as shown below:

As seen from the circuit diagram, the sequential circuit consists of 2 toggle flip flops. As done in the previous circuit, first step is to determine the inputs for the flip flops. And they are

TA = x & B

TB = x

Y= A & B

Now we have studied about toggle flip flops and we know that the next state depends on previous state and the input as

A(t+1) = A(t) xor T

Therefore, here the state outputs are

A(t+1) = (B & x)  xor A

B(t+1) =  x xor B

And the state table for the above circuit is

 

VERILOG CODE:

module digital1(

output y_out, A, B,

input x_in, clock, reset

);

wire TA, TB;

// Flip-flop input equations

assign TA = x_in & B;

assign TB = x_in;

// Output equation

assign y_out = A & B;

// Instantiate Toggle flip-flops

Toggle X(A, TA, clock, reset);

Toggle Y(B, TB, clock, reset);

endmodule




module Toggle(Q, T, CLK, RST_b);

output Q;

input T, CLK, RST_b;

reg Q;

always @ ( posedge CLK, negedge RST_b)

if (RST_b == 0) Q <= 1'b0;

else if (T) Q <= ~Q;

endmodule

RTL SCHEMATIC:

TEST BENCH:

initial begin

                                // Initialize Inputs

                               

                                clock = 1'b1;

                                forever #10

                                clock=~clock;

                                end

               

               

                                initial

                                begin

                                x_in=1;

                                #55;

                                x_in=0;

                                #20;

                                x_in=1;

                                #20;

                                x_in=0;

                                #20;

                               

      end

                               

                                initial

                                begin

                                reset=0;

                                #5;

                                reset=1;

                                end

                                endmodule

 

OUTPUT:

So the same way we analysed previous circuit, we can verify this also with the state diagram.