Today, we will see how to design a sequential circuit using a very basic example, sequence detection. The circuit detects the presence of three or more consecutive 1’s in a string of bits coming through an input line.  So let’s draw the state diagram, which is the preliminary step for the implementation of any sequential circuit. First we have to determine what model we will use, MEALY or MOORE.   Let’s take a Moore Model and design the sequence detector.

Suppose we wish to design a circuit that detects a sequence of three or more consecutive 1’s in a string of bits coming through an input line (i.e., the input is a serial bit stream). The state diagram for this type of circuit is shown in the figure. It is derived by starting with state S0, the reset state. If the input is 0, the circuit stays in S0, but if the input is 1, it goes to state S1 to indicate that a 1 was detected. If the next input is 1, the change is to state S2 to indicate the arrival of two consecutive 1’s, but if the input is 0, the state goes back to S0. The third consecutive 1 sends the circuit to state S3. If more 1’s are detected, the circuit stays in S3. Any 0 input sends the circuit back to S0. In this way, the circuit stays in S3 as long as there are three or more consecutive 1’s received. This is a Moore model sequential circuit, since the output is 1 when the circuit is in state S3 and is 0 otherwise.

STATE ASSIGNMENT:

S0 = 00

S1 = 01

S2 = 10

S3 = 11

After getting the state diagram, determining the characteristic table will be now an easy work, since we know the present state, input, output and the next state. For example, if the state is S0 and input is 0, then the next state is S0 and output 0.

Now we have to determine the next states and the output equations using K-Maps and design the diagram using D flip flops since we will assign Q=D and analyse the inputs.

And here is the design for the sequence detection:

Now, to design it in HDL, we can easily do it using the state diagram as shown below.

VERILOG CODE:

module Moore_Model (

output y_out,

input x_in, clock, reset

);

reg [1: 0] state;

parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10, S3 = 2’b11;

always @ ( posedge clock, negedge reset)

if (reset == 0) state <= S0; // Initialize to state S0

else case (state)

S0: if (x_in) state <= S1; else state <= S0;

S1: if (x_in) state <= S2; else state <= S0;

S2: if (x_in) state <= S3; else state <= S0;

S3: if (x_in) state <= S3; else state <= S0;

endcase

assign y_out = (state == S3); // Output of flip-flops

endmodule

RTL SCHEMATIC:

TEST BENCH:

initial begin

// Initialize Inputs

clock = 1’b1;

forever #10

clock=~clock;

end

initial

begin

x_in=1;

#55;

x_in=0;

#20;

x_in=1;

#20;

x_in=0;

#20;

x_in=1;

#20;

x_in=1;

#20;

x_in=1;

#20;

x_in=1;

#20;

x_in=1;

#20;

x_in=1;

#20;

end

initial

begin

reset=0;

#5;

reset=1;

end

endmodule

OUTPUT:

Therefore, as we see, designing a sequential circuit in VERILOG is very easy since we can design any circuit using only state diagram. You can try designing any other sequence detection using the same methods and verify the same using VERILOG.