MINI PROJECT:TRAFFIC LIGHT CONTROLLER

Having designed a sequential circuit, we are now in a position to design a real time digital circuit using VERILOG. In this blog, we will be designing Traffic Light Controller using Finite State Machine Model: In the sense, we will design the sequential circuit using the state diagram and analyse the circuitry using the RTL Schematic.

We will design the circuit for the 4 way traffic lights, which consists of NORTH, SOUTH, EAST and WEST.

8.PNG

As seen from the state diagram, first the current state will be north green and all the other lights will be off. A counter will run for some amount of time and after that the control will go to the next state, which is the north yellow. Another counter of small duration will run and after the count reaches a specified value, it goes to the south state and the process repeats. I have done the state assignments in the state diagram itself. For green signal, it will show 001; For yellow signal, it will show 010; and for the red signal, it will show 100.

In the VERILOG CODE, first the state assignments are done in first always block, and the other always block consists of output assignments.

VERILOG CODE:

module traffic(n_control,s_control,e_control,w_control,clk,rst_a);

output reg [2:0] n_control,s_control,e_control,w_control;

input clk;

input rst_a;

reg [2:0] state;

parameter [2:0] north=3'b000;

parameter [2:0] north_yellow=3'b001;

parameter [2:0] south=3'b010;

parameter [2:0] south_yellow=3'b011;

parameter [2:0] east=3'b100;

parameter [2:0] east_yellow=3'b101;

parameter [2:0] west=3'b110;

parameter [2:0] west_yellow=3'b111;

reg [2:0] c;

always @(posedge clk, posedge rst_a)

begin

if (rst_a)

begin state=north;

c =3'b000;

end

else

begin

case (state)

north : begin

 if (c==3'b111)

begin

c=3'b000;

state=north_yellow;

end

else

begin

c=c+3'b001;

state=north;

end

end

north_yellow :

begin

if (c==3'b011)

begin

c=3'b000;

state=south;

end

else

begin

c=c+3'b001;

state=north_yellow;

end

end

south :

begin

if (c==3'b111)

begin

c=3'b0;

state=south_yellow;

end

else

begin

c=c+3'b001;

state=south;

end

end

south_yellow :

begin

if (c==3'b011)

begin

c=3'b0;

state=east;

end

else

begin

c=c+3'b001;

state=south_yellow;

end

end

east :

begin

if (c==3'b111)

begin

c=3'b0;

state=east_yellow;

end

else

begin

c=c+3'b001;

state=east;

end

end

east_yellow :

begin if (c==3'b011)

begin

c=3'b0;

state=west;

end

else

begin

c=c+3'b001;

state=east_yellow;

end

end

west :

begin

if (c==3'b111)

begin state=west_yellow;

c=3'b0;

end

else

begin

c=c+3'b001;

state=west;

end

end

west_yellow :

begin

if (c==3'b011)

begin

state=north;

c=3'b0;

end

else

begin

c=c+3'b001;

state=west_yellow;

end

end

endcase // case (state)

end // always @ (state)

end

always @(state)

begin

case (state)

north :

begin n_control = 3'b001;

s_control = 3'b100;

e_control = 3'b100;

w_control = 3'b100;

end // case:north

north_yellow :

begin

n_control = 3'b010;

s_control = 3'b100;

e_control = 3'b100;

w_control = 3'b100;

end // case: north_yellow

south :

begin

n_control = 3'b100;

s_control = 3'b001;

e_control = 3'b100;

w_control = 3'b100;

end // case: south

south_yellow :

begin

n_control = 3'b100;

s_control = 3'b010;

e_control = 3'b100;

w_control = 3'b100;

end // case: south_yellow

west :

begin

n_control = 3'b100;

s_control = 3'b100;

e_control = 3'b100;

w_control = 3'b001;

end // case: west

west_yellow :

begin

n_control = 3'b100;

s_control = 3'b100;

e_control = 3'b100;

w_control = 3'b010;

end // case: west_yellow

east :

begin

n_control = 3'b100;

s_control = 3'b100;

e_control = 3'b001;

w_control = 3'b100;

end // case: east

east_yellow :

begin

n_control = 3'b100;

s_control = 3'b100;

e_control = 3'b010;

w_control = 3'b100;

end // case: east_yellow

endcase // case (state)

end // always @ (state)

endmodule

RTL SCHEMATIC:

9.PNG

10.PNG

So using the Verilog Design, we can analyse what all components to use for the real design of the circuit.

TEST BENCH:

initial begin

                                // Initialize Inputs

                                clk = 1'b1;

                                forever #5

                                clk=~clk;

                                end

                               

                                initial

                                begin

                                rst_a=1'b1;

                                #15;

                                rst_a=1'b0;

                                #1000;

      end

             
                   endmodule

OUTPUT:

11.PNG

The output is self explanatory, First n_contol is GREEN and rest all RED, after 8 clock pulses, it becomes Yellow, and after 4 clock pulses, the control goes to the South signal and it continues till reset is low.

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