A register that goes through a prescribed sequence of states upon the application of input pulses is called a *counter *. The input pulses may be clock pulses, or they may originate from some external source and may occur at a fixed interval of time or at random. The sequence of states may follow the binary number sequence or any other sequence of states. A counter that follows the binary number sequence is called a *binary counter *. An *n *‐bit binary counter consists of *n *flip‐flops and can count in binary from 0 through 2*n *– 1.

Counters are available in two categories: ripple counters and synchronous counters. In a ripple counter, a flip‐flop output transition serves as a source for triggering other flip‐flops. In other words, the *C *input of some or all flip‐flops are triggered, not by the common clock pulses, but rather by the transition that occurs in other flip‐flop outputs. In a synchronous counter, the *C *inputs of all flip‐flops receive the common clock. Synchronous counters are presented in the next two sections. Here, we present the Binary ripple counter and explain its operation.

To understand the operation of the four‐bit binary ripple counter, refer to the first nine binary numbers listed in Table . The count starts with binary 0 and increments by 1 with each count pulse input. After the count of 15, the counter goes back to 0 to repeat the count. The least significant bit, *A*0, is complemented with each count pulse input. Every time that *A*0 goes from 1 to 0, it complements *A*1. Every time that *A*1 goes from 1 to 0, it complements *A*2. Every time that *A*2 goes from 1 to 0, it complements *A*3, and so on for any other higher order bits of a ripple counter.

**VERILOG CODE:**

module counter( input clock,reset, output [3:0]Q ); Toggle A(Q[0],1'b1,clock,reset); Toggle B(Q[1],1'b1,!Q[0],reset); Toggle C(Q[2],1'b1,!Q[1],reset); Toggle D(Q[3],1'b1,!Q[2],reset); endmodule module Toggle(Q, T, CLK, RST_b); output Q; input T, CLK, RST_b; reg Q; always @ ( posedge CLK, negedge RST_b) if (RST_b == 0) Q <= 1'b0; else if (T) Q <= ~Q; endmodule

**RTL SCHEMATIC:**

**TEST BENCH:**

```
initial begin
// Initialize Inputs
clock = 1'b1;
forever #10
clock=~clock;
end
initial
begin
reset=0;
#5;
reset=1;
end
endmodule
```

**OUTPUT:**

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