Serial In Serial Out (SISO) Register

A register is a group of flip‐flops, each one of which shares a common clock and is capable of storing one bit of information. An n ‐bit register consists of a group of n flip‐flops capable of storing n bits of binary information. In addition to the flip‐flops, a register may have combinational gates that perform certain data‐processing tasks. In its broadest definition, a register consists of a group of flip‐flops together with gates that affect their operation. The flip‐flops hold the binary information, and the gates determine how the information is transferred into the register.

gggg.PNG

Consider the SISO register as shown above. The output of a given flip‐flop is connected to the D input of the flip‐flop at its right. This shift register is unidirectional (left‐to‐right). Each clock pulse shifts the contents of the register one bit position to the right. The configuration does not support a left shift. The serial input determines what goes into the leftmost flip‐flop during the shift. The serial output is taken from the output of the rightmost flip‐flop. Sometimes it is necessary to control the shift so that it occurs only with certain pulses, but not with others. As with the data register discussed in the previous section, the clock’s signal can be suppressed by gating the clock signal to prevent the register from shifting. A preferred alternative in high speed circuits is to suppress the clock action, rather than gate the clock signal, by leaving the clock path unchanged, but recirculating the output of each register cell back through a two‐channel mux whose output is connected to the input of the cell. When the clock action is not suppressed, the other channel of the mux provides a datapath to the cell.

VERILOG CODE:

module SISO(

input in,clock,reset,

output T0,T1,T2,T3);

//SISO

DFF A(T0,in,clock,reset);

DFF B(T1,T0,clock,reset);

DFF C(T2,T1,clock,reset);

DFF D(T3,T2,clock,reset);


endmodule

//D FLIP FLOP

module DFF ( output reg Q, input D, Clk, rst);

always @ ( posedge Clk, negedge rst)

if (!rst) Q <= 1'b0;

else Q <= D;

endmodule

RTL SCHEMATIC:

FFFF.PNG

HHHH.PNG

KKKK.PNG

TEST BENCH:

initial begin

                        // Initialize Inputs

                        in = 1;
            end

            initial begin

                        // Initialize Inputs

                        clock = 1'b1;

                        forever #10

                        clock=~clock;

                        end

            initial

                        begin

                        reset=0;

                        #5;

                        reset=1;

                        end

endmodule

OUTPUT:

IIIII.PNG

So as we saw through the VERILOG code, the implementation and design of sequential circuits is very easy once we know the logic and the synthesis is also understandable through the RTL  schematic.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

Powered by WordPress.com.

Up ↑

%d bloggers like this: