IEEE 32 bit Floating Point Subtractor using Verilog

In the previous blogs, I was discussing about floating point adders and multipliers. Subtraction is the same as addition in IEEE Format as well but we need to take care of the sign bits and the shifting of mantissa with respect to the exponent. For the theory behind subtraction, follow the link https://codestall.org/2018/01/11/design-of-32-bit-ieee-floating-point-adder-using-verilog/ , and just... Continue Reading →

Johnson Counter using VERILOG

Johnson counter also known as Switch Tail Counter, consists of shift registers in which the complement of the final register goes as the input for the first register. A Johnson counter is a k ‐bit switch‐tail ring counter with 2 k decoding gates to provide outputs for 2 k timing signals. The eight AND gates... Continue Reading →

RTL SCHEMATIC AND TESTBENCH FOR IEEE FLOATING POINT ADDER

So in the last blog, we saw about the floating point adder ( https://codestall.org/2018/01/11/design-of-32-bit-ieee-floating-point-adder-using-verilog/ ) and its Verilog code. We now have to synthesize it and see the synthesis report. The RTL schematic of the adder is shown below,   TESTBENCH:   module ADDER_v;                 // Inputs                 reg [31:0] a;                 reg [31:0] b;... Continue Reading →

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