Multiplication of two floating-point numbers is done in four steps:

• Non-signed multiplication of mantissas: it must take account of the integer

part, implicit in normalization. The number of bits of the result is twice the

size of the operands (48 bits)

• Normalization of the result: the exponent can be modified accordingly

• Addition of the exponents, taking into account the bias

• Calculation of the sign

Let’s suppose a multiplication of 2 floating-point numbers A and

B, where A=-18.0 and B=9.5

• Binary representation of the operands:

A = -10010.0

B = +1001.1

• Normalized representation of the operands:

A = -1.001×24

B = +1.0011×23

• IEEE representation of the operands:

A = 1 10000011 00100000000000000000000

B = 0 10000010 00110000000000000000000

Multiplication of the mantissas:

• we must extract the mantissas, adding an1 as most significant bit, for

normalization

100100000000000000000000

100110000000000000000000

• the 48-bit result of the multiplication is:

0x558000000000

• only the most significant bits are useful: after normalization (elimination of

the most significant 1), we get the 23-bit mantissa of the result. This

normalization can lead to a correction of the result’s exponent

• in our case, we get:

01 01010110000000000000000 0000000000000000000000

Addition of the exponents:

• Exponent of the result is equal to the sum of the operands exponents. A 1

can be added if needed by the normalization of the mantissas

multiplication (this is not the case in our example)

• As the exponent fields (Ea and Eb) are biased, the bias must be removed in

order to do the addition. And then, we must to add again the bias, to get

the value to be entered into the exponent field of the result (Er):

Er = (Ea-127) + (Eb-127) + 127

= Ea + Eb – 127 = 10000110

Calculation of the sign of the result:

• The sign of the result (Sr) is given by the exclusive-or of the operands signs

(Sa and Sb):

Sr = Sa XOR Sb

• In our example, we get:

Sr = 1 XOR 0 = 1

i.e. a negative sign

• Composition of the result:

the setting of the 3 intermediate results (sign, exponent and

mantissa) gives us the final result of our multiplication:

1 10000110 01010110000000000000000

**VERILOG CODE:**

module multiplier(a,b,out); input[31:0]a,b; output reg [31:0]out; reg [7:0]e_sum,exponent,e1,e2; reg [47:0]prod; reg sign,s1,s2; reg [23:0] product,m1,m2; reg [4:0]i; always @(a or b) begin s1=a[31]; //Sign bit s2=b[31]; e1=a[30:23]; // Exponent bits e2=b[30:23]; m1[23]=1'b1; //Mantissa 24th bit should be 1 m2[23]=1'b1; m1[22:0]=a[22:0]; // Mantissa bits m2[22:0]=b[22:0]; e_sum = e1 + e2 + 1'b1; //Exponent addition exponent=e_sum-8'b01111111; if ( a!=0 || b!=0 ) begin prod=m1*m2; // mantissa product product=prod[47:24]; end if(product == 0) begin out=32'b0; end else begin //Normalization for(i=0;i<23;i=i+1) if (product[23]==0) begin product = product << 1; exponent = exponent - 1; end sign= s1 ^ s2; // Sign Calculation if(a==32'b0 || b==32'b0) // if any input is 0, output is 0 out=0; else out= {sign,exponent,product[22:0]}; // Output end end endmodule

**RTL SCHEMATIC:**

TEST BENCH:

initial begin // Initialize Inputs a = 32'b01000001001000000000000000000000; b = 32'b00000000000000000000000000000000; // Wait 100 ns for global reset to finish #100; end

**OUTPUT:**

Here,

a=10, b=10 ,Therefore result =100 {Refer to ieee online calculator for verification}

## Leave a Reply