Design of 32 bit IEEE Floating Point Adder using VERILOG

Floating Point Addition is performed as
X3 = X1 + X2
X3 = (M1 x 2E1) +/- (M2 x 2E2)

1) X1 and X2 can only be added if the exponents are the same i.e E1=E2.
2) We assume that X1 has the larger absolute value of the 2 numbers. Absolute value of of X1 should be greater than absolute value of X2, else swap the values such that Abs(X1) is greater than Abs(X2).
Abs(X1) > Abs(X2).
3) Initial value of the exponent should be the larger of the 2 numbers, since we know exponent of X1 will be bigger , hence Initial exponent result E3 = E1.
4) Calculate the exponent’s difference i.e. Exp_diff = (E1-E2).
5) Left shift the decimal point of mantissa (M2) by the exponent difference. Now the exponents of both X1 and X2 are same.
6) Compute the sum/difference of the mantissas depending on the sign bit S1 and S2.
If signs of X1 and X2 are equal (S1 == S2) then add the mantissas
If signs of X1 and X2 are not equal (S1 != S2) then subtract the mantissas
7) Normalize the resultant mantissa (M3) if needed. (1.m3 format) and the initial exponent result E3=E1 needs to be adjusted according to the normalization of mantissa.
8) If any of the operands is infinity or if (E3>Emax) , overflow has occurred ,the output should be set to infinity. If(E3 < Emin) then it’s a underflow and the output should be set to zero.
9) Nan’s are not supported.

IEEE 754 standard addition Example:

A = 9.75
B = 0.5625
Equivalent binary words are

 floating point fig13

1) Abs (A) > Abs (B)? Yes. 2) Result of Initial exponent E3 = E1 = 10000010 = 130(10) 3) E1 – E2 = (10000010 – 01111110) => (130-126)=4 4) Shift the mantissa M2 by (E1-E2) so that the exponents are same for both numbers.

 floating point fig14

 

5) Sign bits of both are equal? Yes. Add the mantissa’s

 floating point fig15

6) Normalization needed? No, (if Normalization was required for M3 then the initial exponent result E3=E1 should be adjusted accordingly)
7) Result

 floating point fig16

VERILOG CODE:

module fpadd(a,b,out,e1,e2,exy,s1,s2,sr,sign,m1,m2,mx,my,mxy,mxy2);
input[31:0]a,b;

output reg [31:0]out;
output reg [7:0]e1,e2,exy;
output reg s1,s2,sr,sign;
output reg [23:0]m1,m2,mx,my;
output reg [24:0]mxy,mxy2;
reg [7:0] diff,i,x;
always @ (a or b)
begin
s1=a[31];
s2=b[31];
e1=a[30:23];
e2=b[30:23];
m1[23]=1'b1;
m2[23]=1'b1;
m1[22:0]=a[22:0];
m2[22:0]=b[22:0];




if(e1==e2)
begin
mx=m1;
my=m2;
exy=e1+1'b1;
sign=s1;
end
else if(e1>e2)
begin
diff=e1-e2;
mx=m1;
my=m2>>diff;
exy=e1+1'b1;
sign=s1;
end
else
begin
diff=e2-e1;

mx=m2;
my=m1>>diff;
exy=e2+1'b1;
sign=s2;
end




sr=s1^s2;
if(sr==0)
begin
mxy=mx+my;
sign=s1;
end
else
begin
mxy=mx-my;
end
mxy2=mxy;

if(s1==0 && s2==0)
sign=1'b0;
else if (s1==1 && s2==1)
sign=1'b1;
else if (s1==0 && s2==1)
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b1;
else
sign=1'b0;
end 
else
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b0;
else
sign=1'b1;
end




for(i=0;i<24;i=i+1)

if (mxy[24]==0)
begin
mxy = mxy << 1;
exy = exy - 1;
end

if (mxy[23:0]==24'b0000000000000000000000000)
begin
out=32'b00000000000000000000000000000000;
end
else
begin
out= {sign,exy,mxy[23:1]};
end
end

endmodule

We will see about the execution of this code in the next blog.

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