RTL SCHEMATIC AND TESTBENCH FOR IEEE FLOATING POINT ADDER

So in the last blog, we saw about the floating point adder ( https://codestall.org/2018/01/11/design-of-32-bit-ieee-floating-point-adder-using-verilog/ ) and its Verilog code. We now have to synthesize it and see the synthesis report. The RTL schematic of the adder is shown below,

3

4.PNG

 

TESTBENCH:

 

module ADDER_v;




                // Inputs

                reg [31:0] a;

                reg [31:0] b;




                // Outputs

                wire [31:0] out;

                wire [7:0] e1;

                wire [7:0] e2;

                wire [7:0] exy;

                wire s1;

                wire s2;

                wire sr;

                wire sign;

                wire [23:0] m1;

                wire [23:0] m2;

                wire [23:0] mx;

                wire [23:0] my;

                wire [24:0] mxy;

                wire [24:0] mxy2;




                // Instantiate the Unit Under Test (UUT)

                fpadd uut (

                                .a(a),

                                .b(b),

                                .out(out),

                                .e1(e1),

                                .e2(e2),

                                .exy(exy),

                                .s1(s1),

                                .s2(s2),

                                .sr(sr),

                                .sign(sign),

                                .m1(m1),

                                .m2(m2),

                                .mx(mx),

                                .my(my),

                                .mxy(mxy),

                                .mxy2(mxy2)

                );




                initial begin

                                // Initialize Inputs

                                b = 32'hc0c00000; //-6

                                a = 32'h3f800000;  //1




                                // Wait 100 ns for global reset to finish

                                #100;

       

                               



                end

     

endmodule

 

OUTPUT:

6.PNG

You can verify the output as

a=1; b=-6 ,so the output is -5 (Check using IEEE Calculator )

 

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