In the previous blogs, I was discussing about floating point adders and multipliers. Subtraction is the same as addition in IEEE Format as well but we need to take care of the sign bits and the shifting of mantissa with respect to the exponent.

VERILOG CODE:

```module fpsub(a,b,out,e1,e2,exy,s1,s2,sr,sign,m1,m2,mx,my,mxy,mxy2);
input[31:0]a,b;

output reg [31:0]out;
output reg [7:0]e1,e2,exy;
output reg s1,s2,sr,sign;
output reg [23:0]m1,m2,mx,my;
output reg [24:0]mxy,mxy2;
reg [7:0] diff,i;
always @ (a or b)
begin
s1=a[31];
s2=b[31];
e1=a[30:23];
e2=b[30:23];
m1[23]=1'b1;
m2[23]=1'b1;
m1[22:0]=a[22:0];
m2[22:0]=b[22:0];

//Exponent Calculation

if(e1==e2)
begin
mx=m1;
my=m2;
exy=e1+1'b1;
sign=s1;
end
else if(e1>e2)
begin
diff=e1-e2;
mx=m1;
my=m2>>diff;
exy=e1+1'b1;
sign=s1;
end
else
begin
diff=e2-e1;

mx=m2;
my=m1>>diff;
exy=e2+1'b1;
sign=s2;
end

//Mantissa calculation

sr=s1^s2;
if (sr)
begin
mxy=mx+my;
end
else
begin
mxy=mx-my;
end
mxy2=mxy;

// Sign Calculation

if(s1==0 && s2==0)
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b1;
else
sign=1'b0;
end

else if(s1==0 && s2==1)
sign=1'b0;

else if(s1==1 && s2==0)
sign=1'b1;

else
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b0;
else
sign=1'b1;
end

// Normalisation

for(i=0;i<24;i=i+1)

if (mxy[24]==0)
begin
mxy = mxy << 1;
exy = exy - 1;
end

if (mxy==25'b0000000000000000000000000)
begin
out=32'b00000000000000000000000000000000;
end
else
begin
out= {sign,exy,mxy[23:1]};
end
end

endmodule```

RTL SCHEMATIC:

TEST BENCH:

```                initial begin

// Initialize Inputs

b = 32'hc0c00000;

a = 32'h3f800000;

// Wait 100 ns for global reset to finish

#100;

end

endmodule```

OUTPUT:

Here , a=-1, b=-7 so the output is out= a-b=6 which can be verified using ieee calculator