Johnson Counter using VERILOG

Johnson counter also known as Switch Tail Counter, consists of shift registers in which the complement of the final register goes as the input for the first register.

A Johnson counter is a k ‐bit switch‐tail ring counter with 2 k decoding gates to provide
outputs for 2 k timing signals. The eight AND gates listed in the table, when
connected to the circuit, will complete the construction of the Johnson counter.

9

10

VERILOG CODE

module JOHNSON(
input clock,reset,
output T0,T1,T2,T3);




// Block Level Coding

DFF A(T0,!(T3),clock,reset);
DFF B(T1,T0,clock,reset);
DFF C(T2,T1,clock,reset);
DFF D(T3,T2,clock,reset);

// D flip flop

endmodule
module DFF ( output reg Q, input D, Clk, rst);
always @ ( posedge Clk, negedge rst)
if (!rst) Q <= 1'b0;
else Q <= D;
endmodule

RTL SCHEMATIC:

11

12.PNG

TESTBENCH:

initial begin

                                // Initialize Inputs

                               

                                clock = 1'b1;

                                forever #10

                                clock=~clock;

                                end




                                initial

                                begin

                                reset=0;

                                #5;

                                reset=1;

                                end




endmodule

OUTPUT:

13.PNG

So using Johnson counter, the no of stages can be doubled as compared to ring counter .

 

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