A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter . The input pulses may be clock pulses, or they may originate from some external source and may occur at a fixed interval of time or at random. The sequence of states may follow the... Continue Reading →

A register is a group of flip‐flops, each one of which shares a common clock and is capable of storing one bit of information. An n ‐bit register consists of a group of n flip‐flops capable of storing n bits of binary information. In addition to the flip‐flops, a register may have combinational gates that... Continue Reading →

Having designed a sequential circuit, we are now in a position to design a real time digital circuit using VERILOG. In this blog, we will be designing Traffic Light Controller using Finite State Machine Model: In the sense, we will design the sequential circuit using the state diagram and analyse the circuitry using the RTL... Continue Reading →

Today, we will see how to design a sequential circuit using a very basic example, sequence detection. The circuit detects the presence of three or more consecutive 1’s in a string of bits coming through an input line.  So let’s draw the state diagram, which is the preliminary step for the implementation of any sequential... Continue Reading →

We discussed MEALY MACHINE in our previous blog in which the output depends on input variables as well as the state variables. However in MOORE MACHINE, the output solely depends on state variables. Any change in input which does not make any change to the state values, will not change the output. In Digital Design,... Continue Reading →

So having studied Flip Flops and their operations, it is now the time to start analysing and designing sequential circuits using VERILOG. So in this blog, we are going to analyse a given circuit and try to understand its operations through a state diagram and state table. The time sequence of inputs, outputs and flip... Continue Reading →

The T Flip Flop is a complementing flip flop and can be obtained from a JK FLIP FLOP when J and K inputs are tied together. When T=0, a clock edge does not change the output; the output follows its previous output. However when T=1, the output will be the complement of its previous output.... Continue Reading →

Having studied about D flip flop, one may ask a question as to why to study another flip flop. Well the answer lies here. There are three operations that can be performed using flip flops: Set it to 1, reset it to 0, and complement its output. With only a single input, the D flip... Continue Reading →

The construction of a D Flip Flop with 2 D latches and an inverter is made in order to give it an edge triggered sequential device. The first latch is called the master and the second the slave. The circuit samples the D input and changes its output only at the negative edge of the... Continue Reading →