RTL SCHEMATIC AND TESTBENCH FOR IEEE FLOATING POINT ADDER

So in the last blog, we saw about the floating point adder ( https://codestall.org/2018/01/11/design-of-32-bit-ieee-floating-point-adder-using-verilog/ ) and its Verilog code. We now have to synthesize it and see the synthesis report. The RTL schematic of the adder is shown below,   TESTBENCH:   module ADDER_v;                 // Inputs                 reg [31:0] a;                 reg [31:0] b;... Continue Reading →

Binary Ripple Counter

A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter . The input pulses may be clock pulses, or they may originate from some external source and may occur at a fixed interval of time or at random. The sequence of states may follow the... Continue Reading →

Serial In Serial Out (SISO) Register

A register is a group of flip‐flops, each one of which shares a common clock and is capable of storing one bit of information. An n ‐bit register consists of a group of n flip‐flops capable of storing n bits of binary information. In addition to the flip‐flops, a register may have combinational gates that... Continue Reading →

MINI PROJECT:TRAFFIC LIGHT CONTROLLER

Having designed a sequential circuit, we are now in a position to design a real time digital circuit using VERILOG. In this blog, we will be designing Traffic Light Controller using Finite State Machine Model: In the sense, we will design the sequential circuit using the state diagram and analyse the circuitry using the RTL... Continue Reading →

T FLIP FLOP

The T Flip Flop is a complementing flip flop and can be obtained from a JK FLIP FLOP when J and K inputs are tied together. When T=0, a clock edge does not change the output; the output follows its previous output. However when T=1, the output will be the complement of its previous output.... Continue Reading →

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